INTRODUCTION TO EMBEDDED SYSTEM DESIGN WEEK 8 ASSIGNMENT (NPTEL 2021)
1) Which of the following events will not necessarily trigger a PUC?
a) A CPU instruction fetch from the peripheral address range of 0000H to 01FFH
b) A watchdog timer expiration in any mode
c) A watchdog timer security key violation
d) A Flash memory security key violation
answer) b) A watchdog timer expiration in any mode
2) Which of the following clock sources are not present in MSP430G2553?
a) DCO
b) VLO
c) LFXT1
d) XTCLK
answer) d) XTCLK
3) What is the Default Frequency of DCO in MSP430G2553?
a) 16MHz
b)
d) 1.8MHz
answer) c) 1.1MHz
4) After a POR , which of the following is not an initial device condition ?
a) The RST/NMI pin is configured in the reset mode
b) I/O pins are switched to output mode
c) status register is reset
d) The Watchdog timer powers up in watchdog mode
answer) b) I/O pins are switched to output mode
5) What is the address of Reset Interrupt Vector?
a) Any address from the available memory map
b) 0xFFFE
c) 0xFFFC
d) Reset Interrupt is not a vectored Interrupt
answer) b) 0xFFFE
6) Which of the following flags when '1' represents generation of non - maskable interrupt?
a) ACCVIFG
b) TAIFG
c) OFIFG
d) WDTIFG
answer) a) ACCVIFG , c) OFIFG
7) Global Interrupt Enable bit can affect Non Maskable Interrupt. The statement is
a)
b) False
c)
d) True if the RST/NMI pin is configured in reset mode.
b) False
8) Why do we use #pragma declaration in our code dealing with interrupts?
a)
b)We use it to define the clock frequency
c) We use it to tell the controller that for which interrupt we are writing the subroutine
d)
c) We use it to tell the controller that for which interrupt we are writing the subroutine
9) Arrange the following interrupts in order of their priority (high to low):
1. Oscillator fault
2. Flash memory access violation
3. Timer0_A3
4. Flash key violation
1. Any currently executing instruction is completed
2. PC and SR contents of the main program are stored on Stack
3. SR is cleared.
4. Contents of stack are restored into PC and SR
5. Interrupt flag is cleared (for single source interrupt)
6. Interrupt subroutine code is executed
7. Interrupt with highest priority is selected if multiple interrupts were pending and associated subroutine is selected.
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WEEk 9 assignment solution
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